A conventional MOS (metal-oxide semiconductor) capacitor can be modeled as a parallel plate capacitor. In this type of structure, one plate may be made from a metal or a heavily-doped polycrystalline silicon (“poly”) and one plate may be made from a semiconductor (e.g., the inversion layer formed when the MOS capacitor is under high forward bias). An insulator such as SiO2 or “oxide”, for example, may be used to separate the two plates. In deeply scaled ultra-thin SOI (silicon on insulator) devices, the insulation layer, e.g., oxide, beneath the source and drain regions, is made thinner to improve MOS transistor performance. Although this results in a faster transistor, the thinner channel region and dopant solid solubility limits the amount of active dopants that can be placed in the channel. This results in the effective series resistance becoming quite large in the capacitor. This may pose many problems from a circuit standpoint.
More specifically, in ultra-thin SOI MOS devices, the n-channel FET of the nMOS transistor is made of p-type silicon, and the p-channel FET of the pMOS transistor is made of n-type silicon. Heavily-doped source and drain regions provide electrodes to contact the previously mentioned channel region. In an SOI MOS device, an oxide region is created beneath the channel. The oxide region electrically isolates the source, drain, and channel regions of device from the substrate. The MOS threshold voltage of the channel, i.e., the gate potential when charge carriers can flow through the channel from the source to the drain in significant quantities, is determined by factors such as the work function of the gate, any channel dopants, and the dimensions of the transistor structure. However, low mobile channel charge in a SOI MOS device can under certain conditions have large effective resistance (equivalent serial resistance (ESR)). This large ESR has a great influence on the performance of the capacitor. For example, an increase in the effective resistance of the capacitor will result in worsening frequency characteristics of the capacitor.
A more detailed model of the MOS structure decomposes the vertical gate-dielectric-substrate gate “stack” into two capacitors in series, e.g., a linear oxide capacitance and a nonlinear channel capacitance. By way of example, if the voltage on the gate is strongly negative on an N-type MOS structure, holes are attracted to the dielectric-substrate interface and accumulate there. In the accumulation regime, MOS capacitors act approximately as linear capacitors. On the other hand, if the gate voltage is made positive on an N-type MOS structure, the surface is depleted of mobile holes, creating a depleted region with exposed dopant ions. The depletion capacitance is nonlinear due to the approximately square root dependence of the depletion charge on potential under the gate dielectric. But, as the gate voltage is raised further, the potential barrier between the source terminal and the channel is lower electrostatically and the channel is flooded with mobile electrons from the source. It is the presence of electrons in channel that indicates the inversion of the silicon near the surface, e.g., an NFET channel becomes n-type and analogously a PFET channel becomes p-type.
In the ultra-thin SOI devices, the depth of the silicon region beneath the gate stack is made very thin due to transistor scaling rules, where the bottom of the silicon region beneath the gate is bounded by the buried oxide. Even at channel doping levels near the solid solubility limit, the depletion region induced by the gate can extend from the gate to the back oxide creating a region that is depleted of mobile carriers, (i.e., “fully depleted”).
Weak inversion results when the number of mobile electrons (the inversion charge) is much lower than the number of exposed dopant ions in the depletion region (the depletion charge). On the other hand, strong inversion results when the inversion charge greatly exceeds the depletion charge. Also, the transition between strong inversion to moderate inversion can be defined as the condition when the inversion charge and the depletion charge are comparable. When the channel area under the gate is strongly inverted, the gate charge is balanced out primarily by the inversion layer charge. The voltage at which inversion layer charge dominates is called the threshold voltage Vt and Vt0 indicates the threshold voltage when the source voltage equals zero.
In SOI MOS technologies, there are several modes of operation depending on the application of an external bias to the SOI channel region (also referred to as the silicon body). The silicon body is isolated from the substrate by the buried back oxide. This case, the floating body case, the potential in the body is controlled by many physical factors including diode junction currents from the source and drain, impact ionization near the drain, gate leakage, bipolar effects, and capacitive coupling to the device's electrical terminals the gate, source, drain, and body. An SOI body potential can be defined relative to the source potential and the body potential can be significantly forward-biased with respect to the source potential during normal operation. If an external potential is applied to the SOI body (called a body contact), the body potential is constrained by the external potential and the resistance between the external body contact and the SOI body. Note however that in the case of an ultra-thin SOI device with a silicon body that has been scaled to the point where it is fully-depleted, the external resistance can be so high that the body contact is ineffective.
An extension of the ultra-thin SOI MOS device described above is the dual-gate SOI MOS transistor. In this structure, the back oxide have been thinned to the point that the region below the back oxide can exert non-negligible electrical field on the body and possibly form for an inversion layer or accumulation layer adjacent to the back oxide. When a second gate electrode is placed in or beneath the back oxide, a dual-gate device SOI MOS transistor is formed. Furthermore the second gate electrode (the back gate) is typically isolated from other electrically conductive elements such as the substrate, source, drain, and top gate (front gate).
In conventional MOS process technologies such as SOI or bulk (non-SOI) intentional capacitor circuit elements can be created without significant extra process steps by using a regular MOS transistor that is biased in the inversion or accumulation regime. This gives a relative constant high value capacitor due to the usage of the regular MOS gate oxide. These capacitors can function as decoupling capacitors or as reactive elements in analog applications. However in dual gate ultra-thin SOI the intentional capacitive element formed in this manner can contain parasitic resistance that is dominated by the fully-depleted body in some ranges of operation, reducing it usefulness as a circuit design element. However, traditional and leading-edge circuit design techniques still have a need for intentional capacitive elements, since dual-gate SOI has certain performance advantages over ultra-thin single gate SOI technologies Therefore it is desirable to introduce intentional capacitive circuit elements into dual-gate technologies that are low in parasitic resistance, have high capacitance, and are easy to fabricate.